TEST STRUCTURE FOR ON-CHIP REAL-TIME RELIABILITY TESTING

摘要

PROBLEM TO BE SOLVED: To reduce down time of a system in which an IC is used, by taking out an end-of-life flag before failure occurrs in an active IC. SOLUTION: A system with three on-chip monitoring test structures is used. A first test structure (10) monitors hot carrier degradation. A second test structure (30) monitors TDDB degradation. A third test structure (50) monitors electromigration degradation. Each of these test structures (10, 30 and 50) has logical output level. The logical output level indicates a time at which the test structure has judged that the IC has reached end-of-life. When one of the test structures outputs the end-of-life logical level, an end-of-life indicator (70) outputs a logical level showing that failure will soon occur in the IC so that it is to be exchanged. COPYRIGHT: (C)2004,JPO&NCIPI