发明名称 |
Memory integrated circuit |
摘要 |
An improved memory IC whose memory cells are configured in a chain architecture is disclosed. The first diffusion regions of the cell transistors of the chain are coupled to first capacitor electrodes while the second diffusion regions are coupled to second capacitor electrodes. This ensures that the electric field applied across any of the capacitors of the chain by a plateline pulse is in the same direction. This reduces or avoids asymmetrical hysteresis curves for adjacent memory cells, thereby the improving sensing window.
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申请公布号 |
US6795329(B2) |
申请公布日期 |
2004.09.21 |
申请号 |
US20020177324 |
申请日期 |
2002.06.20 |
申请人 |
INFINEON TECHNOLOGIES AKTIENGESELLSCHAFT |
发明人 |
JACOB MICHAEL |
分类号 |
G11C11/22;H01L21/8246;H01L27/105;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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