| 摘要 |
In order to analyze the conditions leading to a stall or a wait state in a digital signal processing unit, READY signals, that are typically applied to the execution unit of a central processing unit, are applied to external conductors. The external conductors are applied to input terminals of a logic "AND" gate. The output terminals of the logic "AND" gate provided a logic "1" in a no-stall condition and a logic "0" in a stall condition. The output signals of the logic "AND" gate are stored in a memory unit and can be retrieved to determine when a stall condition occurred. The external conductors also apply the READY signal to a stall analyzer unit. The stall analyzer unit identifies the specific condition causing the stall condition by which external conductor has the logic "0" signal applied thereto. An indicia of this stall condition is stored in the memory unit. In event that two conditions are present that can result in a stall condition, a priority unit selected the indicia of a stall condition having the longest duration.
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