| 摘要 |
An isolation signal line in a memory device having a standby power mode is configured to be exclusively held as either a logic high or logic low during some portion of the standby power mode and as the other of the logic high and logic low during another portion of the standby power mode to prevent unnecessary switching every time the memory device operates in standby power mode. As a result, memory devices having an upper and lower array achieve true electrical isolation during standby power modes and, if a row-to-column short exists, standby power mode current leakage is cut in half as compared to non-isolated arrays. The switching current necessary to drive the isolation signal line to a bootstrapped logic high during such standby power mode times is likewise prevented. In other embodiments, methods, electronic systems, wafers and DRAM are taught.
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