发明名称 |
PLL for clock recovery with initialization sequence |
摘要 |
A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
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申请公布号 |
US6794945(B2) |
申请公布日期 |
2004.09.21 |
申请号 |
US20030412448 |
申请日期 |
2003.04.11 |
申请人 |
FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
MCDONALD, II JAMES J.;HULFACHOR RONALD B.;WUNDERLICH JIM |
分类号 |
H03L7/089;H03L7/095;H03L7/099;H03L7/10;H04L7/033;H04L7/04;H04L7/10;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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