发明名称 |
Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design |
摘要 |
A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.
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申请公布号 |
US6795953(B2) |
申请公布日期 |
2004.09.21 |
申请号 |
US20020167039 |
申请日期 |
2002.06.11 |
申请人 |
HPL TECHNOLOGIES, INC. |
发明人 |
BAKARIAN SERGEI;SEGAL JULIE |
分类号 |
G06F17/50;(IPC1-7):G06F17/50;G01R31/305;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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