发明名称 |
Layout technique for address signal lines in decoders including stitched blocks |
摘要 |
A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.
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申请公布号 |
US6795367(B1) |
申请公布日期 |
2004.09.21 |
申请号 |
US20010860031 |
申请日期 |
2001.05.16 |
申请人 |
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发明人 |
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分类号 |
G11C7/00;G11C8/00;H01L27/146;H04N5/335;H04N5/376;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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