| 摘要 |
A programmable delay circuit having a plurality of course delay stages (coupled in series fashion) and a fine delay stage having a plurality of parallel organized delay paths is described, wherein each of the parallel organized delay paths is adapted to receive input from a common course delay stage and to delay a signal for a different specified amount of time. The programmable delay circuit may provide a relatively large overall signal delay (provided primarily by the course delay stages), while also providing a fine temporal resolution (provided primarily by the fine delay stage).
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