| 摘要 |
A memory controller, interface (I/F) device and method for controlling data communication with a memory device are disclosed. The memory controller allows different types of memory devices to be supported. The memory controller has a first buffer for capturing data at a rising edge of a timing control signal and a second buffer for capturing data at a falling edge of the timing control signal. A mode controller controls or adjusts the timing control signal depending on which one of single data rate (SDR) synchronous dynamic random access memory (SDRAM) mode and double date rate (DDR) mode is selected in response to a mode selection or switch signal. In SDR SDRAM mode, a clock signal is supplied to only the first buffer. In DDR mode, a data strobe signal is supplied to both the first and second buffers. The memory controller may also include a level adjuster for adjusting voltage levels of signals transferred between the memory device and buffers.
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