METHOD FOR FORMING TRANSISTOR OF SEMICONDUCTOR DEVICE TO PREVENT ETCH DAMAGE OF N-TYPE TRANSISTOR REGION

摘要

PURPOSE: A method for manufacturing a CMOS(Complementary MOS) transistor is provided to prevent etch damage of an N-type transistor region and to easily control overlap length by forming selectively the first spacer at both sidewalls of a P-type gate pattern. CONSTITUTION: N-type gate patterns(110a) and P-type gate patterns(110b) are formed on an N-type transistor region and a P-type transistor region of a substrate(100). N-type impurities are selectively implanted into the N-type transistor region. The first insulating layer(120a) is formed on the resultant structure. The first spacer(130) is selectively formed at both sidewalls of the P-type gate pattern by etching the first insulating layer of the P-type transistor region while remaining the first insulating layer on the N-type transistor region. P-type impurities are selectively implanted into the P-type gate pattern and the P-type transistor region.