发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS LAY-OUT METHOD
摘要 PROBLEM TO BE SOLVED: To provide a lay-out method of a semiconductor integrated circuit by which higher-level wiring can be disposed easily in a micro-cell. SOLUTION: In this lay-out method of a semiconductor integrated circuit, a semiconductor integrated circuit is laid by using a computer. This method includes a step (a) of arranging two power supply wiring extended in a first direction with a prescribed interval in a first wiring layer provided in the micro-cell, a step (b) of arranging two power supply wiring extended in a second direction which is different from the first direction with a prescribed interval in a second wiring layer provided in the micro-cell, and a step (c) of arranging a plurality of circuit elements constituting the micro-cell and the wiring between the circuit elements. This method also includes a step (d) of arranging signal wiring extended to the outside of the micro-cell through the space formed between the two power supply wiring in the micro-cell in at least either one of the first and second wiring layers. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004259723(A) 申请公布日期 2004.09.16
申请号 JP20030045434 申请日期 2003.02.24
申请人 SEIKO EPSON CORP 发明人 SAKUTA TAKASHI
分类号 G06F17/50;H01L21/3205;H01L21/82;H01L21/822;H01L23/52;H01L27/04;(IPC1-7):H01L21/82;H01L21/320 主分类号 G06F17/50
代理机构 代理人
主权项
地址