发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide technology for suppressing excessive variation in a capacitance value and a resistance value of wiring to find its variation. SOLUTION: This semiconductor integrated circuit design method has: an input step for inputting layout data including one piece of wiring; and an output step for outputting a minimum value and a maximum value of the capacitance value and the resistance value of the one piece of wiring as a predicted value of variation statistics on the basis of the layout data. COPYRIGHT: (C)2004,JPO&NCIPI
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申请公布号 |
JP2004258836(A) |
申请公布日期 |
2004.09.16 |
申请号 |
JP20030046842 |
申请日期 |
2003.02.25 |
申请人 |
FUJITSU LTD |
发明人 |
EJIMA TAKASHI;TAJIMA SHOGO |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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