发明名称 |
Shallow trench isolation for strained silicon processes |
摘要 |
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.
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申请公布号 |
US2004180509(A1) |
申请公布日期 |
2004.09.16 |
申请号 |
US20030389456 |
申请日期 |
2003.03.14 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
WANG HAIHONG;NGO MINH-VAN;XIANG QI;BESSER PAUL R.;PATON ERIC N.;LIN MING-REN |
分类号 |
H01L21/762;H01L21/8234;H01L29/10;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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