| 摘要 |
<p>To analyze the signal delay of a transistor circuit, input signal setting not logically influencing the predetermined operation of the relevant circuit part but influencing the signal delay is effected. Depending on the condition concerning the circuit part, settings excluding the setting of a signal the occurrence possibility of which is zero, the signal setting maximizing the delay, the signal setting minimizing the delay, and signal setting satisfying the actual use condition are effected.</p> |
