| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor having a plurality of instruction sets, facilitating switching of instruction sets. SOLUTION: This processor 100(1) has an instruction set A and an instruction set B. A system instruction decoder 113 decodes a system instruction for specifying an operation mode of the processor, which is included neither in the instruction set A nor in the instruction set B. A system instruction execution control part 114 sets the value of an instruction mode register 115 on receiving the decode result of the system instruction decoder 113 decoding an instruction requesting switching of the instruction sets, and an instruction set switching part 112 selects an instruction set to be used on the basis of the value of the instruction mode register 115. COPYRIGHT: (C)2004,JPO&NCIPI
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