发明名称 |
Scan test control method and scan test circuit |
摘要 |
A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n>1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.
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申请公布号 |
US2004181723(A1) |
申请公布日期 |
2004.09.16 |
申请号 |
US20030722752 |
申请日期 |
2003.11.26 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
NAKAO TOSHINOBU;OZAKI SHINJI;SEZAKI TOMOHISA |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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