发明名称 |
CIRCUIT ARRANGEMENT DESIGN METHOD AND PROGRAM |
摘要 |
<p>A large-scale integrated circuit design includes a step of reading logic and mounting information, a step of performing virtual wiring according to the information, a step of extracting a wiring efficiency improvable portion form the result, a step of performing virtual wiring modification by performing wiring conversion and logic conversion, a step of simulating conversion of the total wiring amount and the signal propagation delay amount accompanying the modification, and a step of obtaining a logic design and mounting design in which the wiring efficiency is improved.</p> |
申请公布号 |
WO2004079598(A1) |
申请公布日期 |
2004.09.16 |
申请号 |
WO2003JP02515 |
申请日期 |
2003.03.04 |
申请人 |
FUJITSU LIMITED;AOKI, KATSUSHI;ITOH, YASUSHI |
发明人 |
AOKI, KATSUSHI;ITOH, YASUSHI |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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