发明名称 DRAM controller with fast page mode optimization
摘要 A system and method for controlling memory accesses for display data. Pixel data for a display are accessed by a graphics controller having two linear counters, the first counter controlling which column is accessed by the controller, the second counter controlling which row is accessed by the controller. With each successive memory access within a predetermined set of accesses, the first counter increments. When the first counter reaches the end of the row in memory (or another predetermined counting state), the second counter increments. When the second counter increments, the controller necessarily accesses the next row of memory locations.
申请公布号 US2004179016(A1) 申请公布日期 2004.09.16
申请号 US20030386299 申请日期 2003.03.11
申请人 KISER CHRIS 发明人 KISER CHRIS
分类号 G09G5/395;(IPC1-7):G09G5/39 主分类号 G09G5/395
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