发明名称 CPU power sequence for large multiprocessor systems
摘要 A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules ("VRM") coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good ("VRMP_G") signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.
申请公布号 US6792553(B2) 申请公布日期 2004.09.14
申请号 US20000751506 申请日期 2000.12.29
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 MAR CLARENCE Y.;OLARIG SOMPONG P.;JENNE JOHN E.
分类号 G06F1/26;G06F1/30;(IPC1-7):G06F1/26 主分类号 G06F1/26
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