发明名称 Differential phase-locked-loop circuit
摘要 A differential charge pump with integrated common-mode control circuitry (100) for a fully differential phase-locked loop is described, having two output lines (OUT+; OUT-) and including a charge pump section (103) and a common-mode feedback section (106). In the charge pump section (103), current generating circuitry (111, 112, 113, 114) generates a first current signal having a first magnitude and a certain polarity on the first signal output (OUT+), and a second current signal having a second magnitude and opposite polarity on the second signal output (OUT-). The common-mode feedback section (106) senses the common-mode voltage level (VCM) of said first and second signal outputs (OUT+, OUT-), compares the common mode voltage (VCM) with a reference voltage (VSET), and generates a feedback signal influencing the current generating circuitry (111, 112, 113, 114) of the charge pump section (103), for increasing/decreasing the first magnitude of the first current signal and simultaneously decreasing/increasing the second magnitude of the second current signal, in order to steer the common-mode voltage level (VCM) towards the reference voltage (VSET).
申请公布号 US6792062(B2) 申请公布日期 2004.09.14
申请号 US20010843500 申请日期 2001.04.26
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V. 发明人 VAUCHER CICERO SILVEIRA
分类号 H03L7/093;H03F3/45;H03L7/089;(IPC1-7):H03D3/24;H03L7/06 主分类号 H03L7/093
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