| 摘要 |
<p>A semiconductor memory characterized by comprising a plurality of bit lines connected, respectively, with a plurality of selected memory cells, a plurality of sense amplifiers connected with one of the plurality of bit lines, a timing circuit generating a signal for activating the plurality of sense amplifiers, respectively, at a different timing, and an output circuit for selecting and delivering up-to-date data, out of data being supplied from the plurality of sense amplifiers at a different timing, in the order of being supplied.</p> |
