发明名称 |
DOUBLE DATA RATE SYNCHRONOUS DRAM SEMICONDUCTOR DEVICE, IN WHICH WRONG WRITING OPERATION IS PREVENTED |
摘要 |
PURPOSE: A DDR(Double Data Rate) synchronous DRAM semiconductor device is provided to prevent data from being read from the inside to the outside of the device when data is written from the outside. CONSTITUTION: According to the DDR(Double Data Rate) synchronous DRAM semiconductor device, a delay locked loop circuit(211) generates an output clock signal by compensating clock skew of an input clock signal. An output part(231) buffers data stored in the DDR synchronous DRAM semiconductor device and then outputs it to the outside of the device. And an output control part(241) disables the output part while the delay locked loop circuit performs a locking operation.
|
申请公布号 |
KR20040078471(A) |
申请公布日期 |
2004.09.10 |
申请号 |
KR20030013423 |
申请日期 |
2003.03.04 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, CHI UK;KIM, GYU HYEON;SEO, SEONG MIN |
分类号 |
G11C11/40;G11C7/10;G11C7/22;G11C8/00;G11C11/407;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/40 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|