SEMICONDUCTOR MEMORY WITH VERTICAL MEMORY TRANSISTORS IN A CELL FIELD ARRANGEMENT WITH 1-2F<2 >CELLS

摘要

The invention relates to a semiconductor memory with a number of memory cells, whereby each of the memory cells comprises four vertical memory transistors with trapping layers. The shallower contact regions are embodied in a semiconductor region running at an angle to the lines and gaps of the cell field, whereby the gate electrode preferably runs on the stage lateral surfaces of the shallower semiconductor region. A memory density of 1-2F<2> per bit may thus be achieved.