发明名称 |
Multilplier and cipher circuit |
摘要 |
A multiplier circuit is disclosed including a Wallace tree block and a carry propagation adder. The Wallace tree block includes a sum calculation block adding partial products for each digit and a carry calculation block adding carries obtained in the addition by the sum calculation block. In the case of multiplication over an extension field (finite field GF(2<n>)) of two, a result of calculation by the sum calculation block is outputted. The carry propagation adder adds the result of calculation by the sum calculation block and a result of calculation by the carry calculation block. In the case of multiplication for integers (finite field GF(p)), a result of calculation by the carry propagation adder is outputted.
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申请公布号 |
US2004177105(A1) |
申请公布日期 |
2004.09.09 |
申请号 |
US20040762174 |
申请日期 |
2004.01.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SATOH AKASHI;TAKANO KOHJI |
分类号 |
G06F7/53;G06F7/52;G06F7/533;G06F7/72;G09C1/00;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/53 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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