| 摘要 |
PROBLEM TO BE SOLVED: To reduce man-hours and errors in test pattern creation for a semiconductor integrated circuit. SOLUTION: This design method for a semiconductor integrated circuit is provided with a net list creation step (S121) for creating a net list, which includes connection information between and inside macros of the semiconductor integrated circuit and identification information about the used macro, and a test pattern creation step (S122) creating a test pattern for the semiconductor integrated circuit on the basis of the identification information about the used macro inside the net list. COPYRIGHT: (C)2004,JPO&NCIPI
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