| 摘要 |
<P>PROBLEM TO BE SOLVED: To realize a semiconductor storage device capable of reducing a subthreshold current at the time of a standby cycle and an active DC current at the time of an active cycle. <P>SOLUTION: A variable impedance power supply line 782 and a variable impedance ground line 783 are set in the state of a low impedance at the time of an active cycle, and set in the state of a high impedance at the time of a standby cycle. A logical gate constituted of MOS (metal oxide semiconductor) transistors PQ, NQ of SOI (silicon on insulator) structures is connected to the power supply line and the ground line. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
