| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock generator capable of changing a frequency so that the lock of a PLL can be prevented from being released. <P>SOLUTION: A frequency transition time automatic setting mode is set (S11), and a timer is set (S12). The value of an increment/decrement quantity setting register(I/D) is set as 1 (S13), and the instruction signal of frequency decrease is set in a P/S pin (S14). Then, a CPU sets the instruction signal of clock frequency increase. Then, the presence/no presence of any malfunction is decided in the PLL (S16), and when any abnormality is not caused (S16; N), time is out (S17), and the processing is ended. On the other hand, when any abnormality is caused (S16; Y), the value of the I/D set at present is set as a default value (S18). Then, 1 is added to the value of the I/D (S19), and a timer is reset (S20), and the processing of the S14 is repeated. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
