| 摘要 |
Single-tone processing in a direct-conversion receiver. The receiver includes a single-tone processing circuit that adds and subtracts gain to prevent saturation of the analog baseband processing circuit as a result of a high single-tone level. The processing circuit includes a single-tone detector that receives quadrature output signals of an I/Q demodulator to detect the signal levels according to predefined signal level criteria. If detected, the detector outputs a digital sign signal that feeds an add/subtractor. The adder/subtractor receives serial input signals from external ASIC's to reduce the gain on a baseband amplifier section, and increase the gain on a following variable gain amplifier section. When the single-tone signal levels drop back to predetermined levels, the amplifier gains are reset to normal operating values.
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