| 摘要 |
The invention relates to a pulse-skipping power converter. In one aspect, a power converter has two stages. When the load is high, both stages are enabled. As the load decreases, one or both of the stages may enter pulse-skipping mode to improve efficiency. As the load is reduced further, the one or both of the stages may be disabled. When both stages are disabled, an auxiliary power supply may be enabled. In a further aspect, an error signal is produced by comparing a signal representative of an output voltage or current of the power converter relative to a level. A pulse-width modulation (PWM) signal including a series of pulses is produced by comparing the error signal to a ramp signal. The duty cycle of the PWM signal is compared to a reference duty cycle. If the duty cycle of the PWM signal is less then the reference duty cycle then the next pulse in the PWM signal is skipped.
|
