| 摘要 |
A system and process for constructing a technology library that is suitable for use with an electronic design automation system that converts the target technology library into a scalable cell library having non-linear, gain-based delay models for estimating circuit delay. The scalable cell library can then be used by gain-based structuring and mapping processes. The library construction process places at least six discrete cells in each logic function of a basic cell set. The library construction process also places at least five discrete cells in each logic function of an extended cell set and rules out cell sizing using internal buffer circuits. Also, for each discrete cell in the complete cell set, the variance of the capacitances between different input pins of the cell is maintained to be within 10 percent. For corresponding timing arcs of discrete sizes for a particular logic function, the present invention keeps equal the ratio of the output load to input capacitance. Also, the present invention constructs a technology library that has geometrically distributed sizes of cells within each logic function. Lastly, for each discrete cell within a logic cluster, the output maximum capacitance constraint is kept linearly proportional to the average input capacitance of the discrete cell. These processes likely allow a technology library to be suitable for the generation of a scalable library which can be used for integrated circuit design and fabrications.
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