| 摘要 |
A latch circuit and method of operation improves the performance of an integrated circuit memory by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information.
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