发明名称 Low weight data encoding for minimal power delivery impact
摘要 A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.
申请公布号 US6788222(B2) 申请公布日期 2004.09.07
申请号 US20010759245 申请日期 2001.01.16
申请人 INTEL CORPORATION 发明人 HALL STEPHEN H.;LEDDIGE MICHAEL W.
分类号 H03M13/00;(IPC1-7):H03M7/00 主分类号 H03M13/00
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