FORMING METHOD OF HIGH-VOLTAGE DUAL GATE DEVICE TO FORM THIN NITRIDE LAYER FOR RESTRICTING LOSS OF ISOLATION LAYER

摘要

PURPOSE: A method for forming a high-voltage dual gate device is provided to restrict damage of an isolation layer by forming a high-voltage gate oxide layer on a selectively etched nitride layer. CONSTITUTION: A high-voltage n-type well region(24) and a high-voltage p-type well region(25) are formed on a high-voltage device region of a semiconductor substrate(21). A source/drain region(26) of an NMOS transistor and a source/drain region(27) of a PMOS transistor are formed within the high-voltage n-type well region and the high-voltage p-type well region, respectively. An isolation layer is formed on an isolation region by performing an STI process. A buffering nitride layer(32) is formed thereon. A high-voltage gate oxide layer(33) is formed on the high-voltage device region of the buffering nitride layer. A low-voltage p-type well region and a low-voltage n-type well region are formed within a low-voltage device region of the semiconductor substrate. A low-voltage gate oxide layer(36) is formed thereon.