SYSTEM AND METHOD FOR INTEGRATING PLURAL METAL GATES IN CMOS APPLICATION TO SET THRESHOLD VOLTAGE BY USING STACKED METAL GATE STRUCTURE

摘要

PURPOSE: A method for integrating a plurality of metal gates in CMOS(complementary metal oxide semiconductor) application is provided to form a desired threshold voltage by forming a metal gate stack without etching the first metal in the stack wherein damage to a gate dielectric located under the stack is minimized. CONSTITUTION: A dual gate MOSFET(metal-oxide-semiconductor field-effect-transistor) has a metal gate. A gate oxide layer(114,116) positioned on the first and second channel regions(110,112) is formed. The first metal layer with the first thickness is formed on the gate oxide layer. The second metal layer with the second thickness is formed on the first metal layer with the first thickness. The second metal layer above the first channel region is selectively eliminated. The first MOSFET with a gate work function is formed along the thickness of the first metal layer formed above the first channel region. The second MOSFET that has a gate work function and is complementary to the first MOSFET is formed along the combination of the thickness of the first and second metal layers formed above the second channel region.