EXPENDABLE VERIFICATION CODE USING FPGA OF SOC HAVING ARM CORE, FOR REALIZING SOC VERIFICATION BOARD HAVING VARIOUS FUNCTIONS

摘要

PURPOSE: An expendable verification code using the FPGA(Field Programmable Gate Arrays) of an SOC(System-On-Chip) having an ARM(Advanced RISC Machine) core is provided to realize an SOC verification board having various functions by changing the ARM core or adding the IPs(Intellectual Property) if necessary. CONSTITUTION: An ARM core connector(120) includes the core connectors supporting the connection of diverse kinds of ARM cores. A first FPGA board(110) connects with the ARM core connector through the AHB(Advanced High-performance Bus) and realizes the system IPs communicating with the ARM core. A second FPGA board(150) connects with the first FPGA through the APB and realizes peripheral IPs. An extended connector(140) connects with the first FPGA through the APB(Advanced Peripheral Bus) and the AMBA(Advanced Microcontroller Bus Architecture), and supports the connection of the additional IPs. A memory(130) stores the communication data between the ARM core and the system IPs.