| 摘要 |
The present invention relates to a memory cell having a quasi-folded bit line sensing arrangement with an open bit line cell array. The memory cell array noise is negligible compared to the conventional open bit line. Also, the twisted bit line structure can be applied for the invention to reduce the inter-bit line coupling noise. The embodiments of the present invention reduce the size of the edge array, reduce the sensing power requirements, and provide a simple bit line layout. According to one embodiment of the present invention, a memory device comprises a plurality of sense amplifiers, each sense amplifier enabling access to data associated with arrays of cells; a bit line pair being coupled to each sense amplifier and comprising a bit line and a complementary bit line; a plurality of word lines associated with an array of cells; and a plurality of switches is employed to enable access to memory cells of the memory device. The arrangement of the memory device enables a VBLEQ signal to be coupled directly to the bit lines and complementary bit lines of the memory device. An improved sense amplifier having precharge circuit of a single transistor is also described. According to another aspect of the present invention, a method of reading and writing data in a memory device is described. The method comprises providing a bit line pair having a bit line and a complementary bit line, and coupling the bit line pair to a plurality of sense amplifiers. A plurality of switches is also provided in the bit line pair. The plurality of switches enables access to a memory cell to enable reading and writing data in the memory cell.
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