发明名称 SEMICONDUCTOR RELIABILITY EVALUATING DEVICE AND EVALUATING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor reliability evaluating device equipped with a wiring layer electromigration characteristic evaluation pattern which is easily formed at a low cost using a minimum reticle set that has two wiring layers and is capable of measuring usual via resistance, and to provide an evaluation method. SOLUTION: The semiconductor reliability evaluating device has a wiring structure composed of a first wiring layer and a second wiring layer which are connected to each other through a plurality of vias formed in an insulating layer interposed between the wiring layers. The first wiring layer and the second wiring layer are formed of metals which are nearly equivalent in resistivity to each other, and different parasitic resistors are added to the first wiring layer and/or the second wiring layer connected to the vias so as to enable the total resistance of current routes passing through each of the vias to differ from each other. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004247360(A) 申请公布日期 2004.09.02
申请号 JP20030032915 申请日期 2003.02.10
申请人 NEC ELECTRONICS CORP 发明人 SAITO YUMI;TSUDA KOJI
分类号 H01L21/66;H01L21/3205;H01L21/768;H01L21/822;H01L23/52;H01L23/528;H01L23/544;H01L27/04;(IPC1-7):H01L21/66;H01L21/320 主分类号 H01L21/66
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