| 摘要 |
<p>A clock generating circuit includes a plurality of delay lines connected in cascade, each delay line including two switching elements for letting in or shutting out a clock, and a delay element connected to each of the switching elements. A PLL circuit and a semiconductor device both include the clock generating circuit. The number K of the delay units in each of the delay lines of the clock generating circuit is calculated from: <MATH> <IMAGE></p> |
