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发明名称
半导体装置之制造方法
摘要
本发明系关于一种半导体装置之制造方法,其目的在于提高沟渠形成用抗蚀剂图案的尺寸控制性。其解决手段系在覆盖铜内连线1之层间绝缘膜2内,形成连接于铜内连线1之穿孔3。利用电气分解在穿孔3内埋设导电性高分子4。在层间绝缘膜2上利用光微影形成抗蚀剂图案5,并将抗蚀剂图案5当作遮罩而利用蚀刻形成连接于穿孔3之沟渠6。此后,去除抗蚀剂图案5及导电性高分子4。
申请公布号
TW200416791
申请公布日期
2004.09.01
申请号
TW092131773
申请日期
2003.11.13
申请人
瑞萨科技股份有限公司
发明人
齐藤隆幸
分类号
H01L21/00;H01L21/768
主分类号
H01L21/00
代理机构
代理人
赖经臣
主权项
地址
日本
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