| 摘要 |
In a phase locked loop type frequency synthesizer including a phase/frequency comparator (1) for receiving an input signal (IN), a charge pump circuit (2), a loop filter (3) for generating a control voltage (VC), a voltage control oscillator block (4') including a plurality of voltage controlled oscillators (41'-0, 41'-1, 41'-2, ..., 41'-(m-1)) controlled by the control voltage, and a frequency divider formed by a fixed frequency divider (51') and a programmable frequency divider (52'), a selecting circuit (7', 8') selects and activates only one of the voltage controlled oscillators, and counts the number (Sf) of output pulses of the first frequency divider within a predetermined number (RO) of output pulses of the input signal while applying a bias voltage to the loop filter. Thus, the one of the voltage controlled oscillators being selected so that the number of the output pulses of the first frequency divider is brought close to an optimum value (Sopt). <IMAGE>
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