CHIP SCALE PACKAGE HAVING REDUCED SIZE CORRESPONDING TO SIZE OF SEMICONDUCTOR CHIP AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A chip scale package and a fabricating method thereof are provided to reduce the manufacturing cost by reducing the thickness and the size of the chip scale package. CONSTITUTION: A passivation layer(204) is formed on an upper surface of a semiconductor chip(200) to expose a bonding pad(202). An insulating tape(206) is adhered on the passivation layer in order to expose the bonding pad. A through-hole is formed on the insulating tape corresponding to the bonding pad. An adhesive(208) is coated on a bottom surface of the insulating tape. A connection terminal(210) is formed on an upper surface of the insulating tape around the through-hole. A conductive layer is formed on the bonding pad within the through-hole. A solder ball(220) is adhered on the conduction terminal and the conductive layer.