Fixed-logic signal generated in an integrated circuit for testing a function macro integrated in an integrated circuit

摘要

A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm+1 to Sn) to input terminals (INm+1 to INn) of a function macro (1) for receiving signals whose logic levels are fixed to "H" or "L" on at least one test pattern. This eliminates any external input terminal for inputting such fixed-logic signal. When the integrated circuit includes function macros, they can be simultaneously tested with this construction.