发明名称 Power on reset circuit
摘要 A POR circuit includes a signal generator which has a PMOS transistor and a first and second resistors connected in series. The PMOS transistor is controlled in accordance with a DPWD signal. A first signal obtained by dividing a voltage difference between the ground voltage and the supply voltage is output from a first node between the first and second resistors. The POR circuit also includes an edge generator which includes a third resistor and an NMOS transistor connected in series, and an inverter coupled to a second node between the third resistor and the NMOS transistor. The NMOS transistor is controlled in accordance with a voltage of the first signal output from the first node. When the NMOS transistor turns on, a second signal having an edge waveform is generated at the second node, the first inverter outputs a third signal which is a reversal of the second signal. The POR circuit also includes a delay circuit which receives the DPWD signal and outputs a DLDPWD signal, a charging circuit which is connected in parallel to the first resistor so that the first node can be charged, and an output inhibit circuit which outputs an edge waveform contained in the third signal as a reset signal when changing from the power-off state to the power-on state, and does not output the reset signal when the voltage of the DPWD signal changes from high to low.
申请公布号 US6784705(B2) 申请公布日期 2004.08.31
申请号 US20030352229 申请日期 2003.01.28
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 KAMATA YOSHIHIKO
分类号 G06F1/24;H03G3/34;H03K17/22;(IPC1-7):H03L7/00 主分类号 G06F1/24
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