发明名称 Lock detection system for use in high speed communication systems
摘要 A lock detection method for generating a lock signal including providing a data signal and a clock signal to a clock detection unit, the data signal being describable by an eye pattern, the data signal and the clock signal being in lock when a data transition occurs in the center of a first transition period. A lock detection unit including: detection of absence or presence of a data transition of the data signal in a first partial period centered around the center of the first transition period and generating a first output signal having a first logic value in response to the presence of a data transition and having a second logic value in response to the absence of a data transition in the first partial period, detection of absence or presence of a data transition of the data signal in a second partial period centered around the center of the eye and generating a second output signal having a first logic value in response to the absence of a data transition and having a second logic value in response to the presence of a data transition in the second partial period, and comparing the first and second output signals and generating a lock signal according to the comparison.
申请公布号 US6785354(B1) 申请公布日期 2004.08.31
申请号 US20000722337 申请日期 2000.11.28
申请人 INTEL CORPORATION 发明人 DIETRICH CASPER
分类号 H03D13/00;H03L7/087;H03L7/089;H03L7/091;H03L7/095;H03L7/12;H04L7/033;(IPC1-7):H03D3/24 主分类号 H03D13/00
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