| 摘要 |
A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. In one particular embodiment of the present invention, a logic structure having PFET pullups (402, 406, and 410) and NFET pulldowns (404, 408, and 412), receives active low pulsed input signals (A, B, and C) and produces a logical high output signal (D) when all the input signals are at a low level. When at least one, but not all, of the input signals (A, B, and C) are low, the logic structure produces a logical low output signal (D), while sinking a DC current. When all of the input signals (404, 408, and 412) are at a high level, which is the default condition for this particular embodiment, the logic structure produces a logical low output signal (D), and no DC current paths are switched on.
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