Testing method and device for non-volatile memories having a LPC (low pin count) communication serial interface

摘要

An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.