发明名称 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE TO IMPROVE DIMENSION CONTROLLABILITY OF RESIST PATTERN FOR FORMING TRENCH
摘要 PURPOSE: A method for fabricating a semiconductor device is provided to improve dimension controllability of a resist pattern for forming a trench by preventing a filling material in the surface of a substrate from varying. CONSTITUTION: A via hole(3) connected to a basic interconnection(1) is formed in an interlayer dielectric(2) coating the basic interconnection. Conductive polymer(4) is formed in the via hole by an electroanalysis method. A resist pattern(5) is formed on the interlayer dielectric. A trench(6) connected to the via hole is formed by an etch process using the resist pattern as a mask.
申请公布号 KR20040075708(A) 申请公布日期 2004.08.30
申请号 KR20040002543 申请日期 2004.01.14
申请人 RENESAS TECHNOLOGY CORP. 发明人 SAITO TAKAYUKI
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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