发明名称 METHOD FOR FABRICATING ELECTRONIC DEVICE TO CONTROL RESOLUTION DEFECT OF RESIST PATTERN AND REDUCE DEFECTIVE INTERCONNECTION CAUSED BY RESOLUTION DEFECT
摘要 PURPOSE: A method for fabricating an electronic device is provided to reduce byproducts by performing a heat treatment after a hole passing through an interlayer dielectric is formed and by discharging the byproduct on an interface between an etching stopper layer and the interlayer dielectric. CONSTITUTION: The interlayer dielectric is selectively eliminated. A hole is formed that passes through the interlayer dielectric and reaches the etching stopper layer(4). A heat treatment is performed while the hole is open. The hole is filled with organic resin cured by deep ultraviolet rays, and the organic resin is cured by the deep ultraviolet rays to form a buried plug. The interlayer dielectric and the buried plug are selectively removed by using chemical amplification type resist as an etching mask, and a groove pattern for burying an upper interconnection is formed in the upper main surface of the interlayer dielectric. The buried plug left in the hole is eliminated to connect the groove pattern with the hole. The etching stopper layer is selectively removed to expose a lower interconnection(20). The groove pattern and the hole are filled with a conductive material to form the upper interconnection and a contact part simultaneously.
申请公布号 KR20040075688(A) 申请公布日期 2004.08.30
申请号 KR20030087196 申请日期 2003.12.03
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;RENESAS TECHNOLOGY CORP. 发明人 NISHIOKA YASUTAKA;SAKAI JUNJIRO;TOMOHISA SHINGO;MATSUMOTO SUSUMU;IWAMOTO FUMIO;YAMANAKA MICHINARI
分类号 H01K3/10;H01L21/768;H05K3/10;(IPC1-7):H01L21/768 主分类号 H01K3/10
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