发明名称 |
Semiconductor device and manufacturing method thereof |
摘要 |
Interfaces between an Al alloy layer and a Ti-containing layer are present in a through hole formed between a lower layer interconnection and an upper layer interconnection. In the interfaces, resistance element regions are formed through heat treatment. A resistance value between the lower layer interconnection and the upper layer interconnection can be adjusted by means of the resistance element region.
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申请公布号 |
US2004164417(A1) |
申请公布日期 |
2004.08.26 |
申请号 |
US20030642170 |
申请日期 |
2003.08.18 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
YAMASHITA YASUNORI;HATASAKO KENICHI |
分类号 |
H01L21/768;H01L21/02;H01L21/82;H01L21/822;H01L23/522;H01L23/525;H01L27/04;(IPC1-7):H01L23/48 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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