发明名称 |
Semiconductor memory with vertical charge-trapping memory cells and fabrication |
摘要 |
Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.
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申请公布号 |
US2004164345(A1) |
申请公布日期 |
2004.08.26 |
申请号 |
US20030741970 |
申请日期 |
2003.12.19 |
申请人 |
KLEINT CHRISTOPH;DEPPE JOACHIM;LUDWIG CHRISTOPH;SACHSE JENS-UWE |
发明人 |
KLEINT CHRISTOPH;DEPPE JOACHIM;LUDWIG CHRISTOPH;SACHSE JENS-UWE |
分类号 |
H01L21/8247;H01L21/28;H01L21/336;H01L21/8234;H01L21/8246;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/792 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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